The prior art contains a number of switched-capacitor architectures suitable for use in practical applications such as filters, gain amplifiers, and analog-to-digital converters (“ADCs”). Briefly, switched-capacitor gain stages provide precisely defined gains determined by a ratio in values between capacitors, where the capacitors are used to sample an input signal. In one type of switched-capacitor gain stage, a pair of capacitors is charged in parallel across an input voltage and a ground reference. The capacitor terminals that are coupled to the ground reference are then moved to the inverting input of an operational amplifier while one of the capacitor terminals previously coupled to the input voltage is switched to the output of the amplifier and the other capacitor terminal previously coupled to the input voltage is switched to a reference voltage. When the capacitors have the same value, the output of the amplifier will then be twice the input voltage, modified by the addition or subtraction of the reference voltage (depending upon the polarity of the reference voltage). In order to increase the throughput of the gain stage, two sets of capacitor pairs may be used with one charging from the input voltage while the other is connected to the operational amplifier to produce an output value.
FIG. 1 depicts a prior art double sampled switched-capacitor architecture 100, along with example clock/control signals that influence the operation of switched-capacitor architecture 100. For simplicity, the schematic shown in FIG. 1 is depicted in a single-ended configuration. Switched-capacitor architecture 100 generally includes an amplifier 102, a first switched-capacitor arrangement 104, a second switched-capacitor arrangement 106, a first digital logic component 108, and a second digital logic component 110. The digital logic components generate switch control signals for the switched-capacitor arrangements. Switched-capacitor architecture 100 also includes an input node 112 for receiving an input voltage signal, an output node 114 for providing a voltage sample sequence that is derived from the input voltage signal, a first reference node 116 for a first reference voltage VREFP, and a second reference node 118 for a second reference voltage VREFM.
The switches are controlled by the p1 and p2 clock signals depicted in FIG. 1 and by the switch control signals generated by digital logic components 108/110. The switches in FIG. 1 are labeled with their respective governing clock/control signals. In this example, when a clock/control signal is high, the associated switch is closed, and when a clock/control signal is low, the associated switch is open. Thus, when the p1 clock signal is high and the p2 clock signal is low, the C1i and C2i capacitors charge to sample the input voltage applied to input node 112. In addition, the C1q and C2q capacitors are coupled to amplifier 102, which generates an output voltage at output node 114. Moreover, either the hq switch, the lq switch, or the mq switch is closed depending upon the comparison of the input voltage present at input node 112 relative to a high voltage reference (VH) and a low voltage reference (VL). The output voltage at output node 104 will depend upon which of these three switches is closed.
When the p1 clock signal is low and the p2 clock signal is high, the C1q and C2q capacitors charge to sample the input voltage applied to input node 112. In addition, the C1i and C2i capacitors are coupled to amplifier 102, which generates an output voltage at output node 114. Moreover, either the hi switch, the li switch, or the mi switch is closed depending upon the comparison of the input voltage present at input node 112 relative to VH and VL. The output voltage at output node 114 will depend upon which of these three switches is closed.
In double sampled switched-capacitor architectures, both switch networks share the same input section of the amplifier (as depicted in FIG. 1). FIG. 1 shows a parasitic capacitance Cp that represents a capacitance that is inherent to a practical amplifier 102 that utilizes a differential transistor pair as its input section. In such an architecture there is no opportunity to auto-zero amplifier 102 between output phases because an output sample is generated for each available clock phase. Consequently, a residue charge remains at the summing junction of amplifier 102 from phase to phase, and that residue charge results in gain error for amplifier 102. This problem is caused by the sharing of charge on the parasitic capacitance by both switch networks. In a practical embodiment, this error limits the overall accuracy of the switched-capacitor architecture 100.
One possible solution to the problem discussed above is to increase the bandwidth of the amplifier to accommodate additional clock phases during which auto-zeroing can be performed. This proposed solution may not be desirable in practical applications because the proposed solution increases power dissipation and area needed to meet the gain bandwidth product for the application. Moreover, the additional clock phases causes issues with increased clock feed through and charge injection due to the increased switch area needed to accommodate the higher clock rate. This approach increases the overall area of the amplifier, switches, and possibly the capacitor array. Another possible solution to this problem is to utilize two separate channels and, hence, two distinct amplifiers. This proposed solution may not be desirable for practical applications that strive to reduce device size and complexity. For example, the use of separate channels increases the area and power dissipation of the system, due to the use of additional amplifiers.
Accordingly, it is desirable to have an amplifier circuit, suitable for use in a double sampled switched-capacitor architecture, that reduces the gain error that would otherwise be caused by residual parasitic capacitance at the input of the amplifier circuit. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.